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PACVGA100/101 VGA Port ESD Protection and Termination Network
Features
* * * Seven channel ESD protection
+15 kV ESD protection per channel, connector
Product Description
The PACVGA100/101 functions as a transmission line termination and ESD protection device for video applications. It provides 75 ohm parallel terminations for video R, G, and B lines and series terminations for the Horizontal Sync, Vertical Sync and the two DDC lines which serve as Plug and Play logic signals. In addition, all interface lines provide Level 4 ESD protection per the IEC 61000-4-2 contact discharge specification. The PACVGA100 provides internal pull-up resistors (R3) for the two DDC lines whereas the PACVGA101 omits these internal pull-ups so that different pull-up resistor values can be added externally.
side (HBM)
+8 kV contact, 15 kV air discharge ESD protection
* *
per channel, connector side (IEC 61000-4-2 Level 4 standard) Low loading capacitance--4.5pF typical 16-pin QSOP package
Applications
* * * * ESD protection and termination resistors for VGA (video) port interfaces Desktop PCs Notebook computers LCD monitors
Typical Application Circuit
Simplified Electrical Schematic
VCC R1, R2 required only for VGA101
(See Note 1)
R G B VCC CBYPASS 0.2uF
1
8
16
Video Controller
Red Grn Blue H-Sync V-Sync DDC_Data DDC_Clk
2 3 5 7 9 11 14
PACVGA100/101
6 10 12 15
Video Connector
H-Sync V-Sync DDC_Data DDC_Clk
R1
R2
4
13
Note 1: For best ESD protection, minimize R/G/B trace lengths between the PACVGA100/101 device and the video connector.
R1 = 75, R2 = 33 R3 = 2.2K (for PACVGA100 only)
* R3 omitted for PACVGA101
(c) 2002 California Micro Devices Corp. All rights reserved. 02/14/02
215 Topaz Street, Milpitas, California 95035
L Tel: (408) 263-3214
L Fax: (408) 263-7846 L
www.calmicro.com
1
PACVGA100/101
PACKAGE / PINOUT DIAGRAM
Top View
VCC RGB1 RGB2 VSS RGB3 SYNC1_CONN SYNC1_CTLR VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC DDC2_CONN DDC2_CTLR VSS DDC1_CONN DDC1_CTLR SYNC2_CONN SYNC2_CTLR
Note: This drawing is not to scale.
16-pin QSOP
PIN DESCRIPTIONS
LEAD(s) 1, 8, 16 2 3 4, 13 5 6 7 9 10 11 12 14 15 NAME VCC RGB1 RGB2 VSS RGB3 SYNC1_CONN SYNC1_CTLR SYNC2_CTLR SYNC2_CONN DDC1_CTLR DDC1_CONN DDC2_CTLR DDC2_CONN DESCRIPTION Positive voltage supply pins. RGB Video Protection Channel 1. Ties to one of the RGB video lines (for example, the Red signal) between the VGA controller device and the video connector. RGB Video Protection Channel 2. Ties to one of the RGB video lines (for example, the Blue signal) between the VGA controller device and the video connector. Ground reference supply pin. RGB Video Protection Channel 3. Ties to one of the RGB video lines (for example, the Green signal) between the VGA controller device and the video connector. Sync Signal Output 1. Ties to the video connector side of one of the sync lines (for example the Horizontal Sync signal). Sync Signal Input 1. Connects to the VGA Controller side of one of the sync lines (for example, the Horizontal Sync signal). Sync Signal Input 2. Connects to the VGA Controller side of one of the sync lines (for example, the Vertical Sync signal). Sync Signal Output 2. Connects to the video connector side of one of the sync lines (for example, the Vertical Sync signal). DDC Signal Input 1. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). DDC Signal Output 1. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). DDC Signal Input 2. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Clk). DDC Signal Output 2. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Clk).
(c) 2002 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035 L Tel: (408) 263-3214 L Fax: (408) 263-7846 L www.calmicro.com
02/14/02
PACVGA100/101
Ordering Information
PART NUMBERING INFORMATION
Pins 16 16 Package QSOP QSOP Ordering Part Number1 PACVGA100 PACVGA101 Part Marking PACVGA100Q PACVGA101Q
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VCC - VSS) Diode Forward DC Current (Note 1) Operating Temperature Range Storage Temperature Range DC Voltage at any channel input Package Power Rating
Note 1: Only one diode conducting at a time.
RATING 6.0 20 -40 to +85 -65 to +150 (V SS - 0.5) to (VCC + 0.5) 800
UNITS V mA C C V mW
STANDARD OPERATING CONDITIONS
PARAMETER Operating Temperature Range Operating Supply Voltage (VCC- VSS) PACVGA100 PACVGA101 RATING -40 to +85 5.0 3.3 to 5.0 UNITS C V V
(c) 2002 California Micro Devices Corp. All rights reserved. 02/14/02
215 Topaz Street, Milpitas, California 95035
L Tel: (408) 263-3214
L Fax: (408) 263-7846 L
www.calmicro.com
3
PACVGA100/101
Specifications (cont'd)
ELECTRICAL OPERATING CHARACTERISTICS1
SYMBOL TOLR PARAMETER Resistor Absolute Tolerance R/G/B Termination Resistor (R1) Series Termination Resistor (R2) DDC Pull-up Resistor (R3) Temperature Coefficient of Resistance (TCR) Diode Forward Voltage Diode Reverse Breakdown Voltage Top Diode (Cathode connected to VCC) Bottom Diode (Anode connected to VSS) Channel Leakage Current Channel Input Capacitance at pins 2, 3, 5, 6, 10, 12 & 15 @ 1 MHz, VP=5V, V N=0V, VIN=2.5V; Note 2 applies Note 3 Notes 2,4 Notes 2,5 Note 6 Notes 2,4 @15kV ESD HBM; Notes 2 & 4 +15 +8 +4 kV kV kV IF = 20mA 0.65 17.0 25.0 +0.1 4.5 +1.0 6 CONDITIONS MIN TYP MAX +5 +5 +10 +200 0.95 UNITS % % % ppm/C V V V A pF
TCR VF VRB
ILEAK CIN
VESD
ESD Protection 1) Peak Discharge Voltage at pins 2, 3, 5, 6 10, 12 & 15, in system a) Human Body Model, MIL-STD-883, Method 3015 b) Contact discharge per IEC 61000-4-2 2) Peak Discharge Voltage at pins 7, 9, 11 & 14 a) Human Body Model, MIL-STD-883, Method 3015
VCP
Channel Clamp Voltage at pins 2, 3, 5, 6, 10, 12 & 15 Positive Transients Negative Transients
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
VP + 13.0 VN - 13.0
V V
All parameters specified at TA=25C unless otherwise noted. These parameters guaranteed by design and characterization. From I/O pins to VP or VN only; VP bypassed to VN with 0.2F ceramic capacitor. Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, R Discharge = 1.5K, VP = 5.0V, VN grounded. Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330, VP = 5.0V, VN grounded. These pins are not directly connected to the VGA connector and therefore are not subject to direct ESD strikes.
(c) 2002 California Micro Devices Corp. All rights reserved.
4
215 Topaz Street, Milpitas, California 95035 L Tel: (408) 263-3214 L Fax: (408) 263-7846 L www.calmicro.com
02/14/02
PACVGA100/101
Mechanical Details
QSOP Mechanical Specifications PACVGA100/101 devices are packaged in 16-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-16 package, see the California Micro Devices QSOP Package Information document. Mechanical Package Diagrams
TOP VIEW
D
16 15 14 13 12 11 10 9
PACKAGE DIMENSIONS
Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.35 0.10 0.20 0.18 4.80 3.81 5.79 0.40 Max 1.75 0.25 0.30 0.25 5.00 3.98 6.19 1.27 Min 0.053 0.004 0.008 0.007 0.189 0.150 0.228 0.016 QSOP (JEDEC name is SSOP) 16 Inches Max 0.069 0.010 0.012 0.010 0.197 0.157 0.244 0.050
C
END VIEW SIDE VIEW 1 2 3 4 5 6 7 8
H
Pin 1 Marking
E
A
SEATING PLANE
A1 B e
0.64 BSC
0.025 BSC
100 pieces* 2500 pieces Controlling dimension: inches
L
* This is an approximate number which may vary.
Package Dimensions for QSOP-16
(c) 2002 California Micro Devices Corp. All rights reserved. 02/14/02
215 Topaz Street, Milpitas, California 95035
L Tel: (408) 263-3214
L Fax: (408) 263-7846 L
www.calmicro.com
5

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